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CS4360 24-Bit, 192 kHz 6-channel D/A Converter
Features
24-bit Conversion 102 dB Dynamic Range -91 dB THD+N Low Clock Jitter Sensitivity Digital Volume Control with Soft Ramp
- 119 dB Attenuation - 1-dB Step Size - Zero Crossing Click-Free Transitions
Description
The CS4360 is a complete 6-channel digital-to-analog system including digital interpolation, fourth-order deltasigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing and analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, and a high tolerance to clock jitter. The CS4360 accepts data at audio sample rates from 4 kHz to 200 kHz, consumes very little power, and operates over a wide power supply range. These features are ideal for cost-sensitive, multi-channel audio systems including DVD players, A/V receivers, set-top boxes, digital TVs and VCRs, mini-component systems, and mixing consoles. ORDERING INFORMATION CS4360-KZ -10 to 70 C 28-pin TSSOP CS4360-KZZ -10 to 70 C Lead Free 28-pin TSSOP CS4360-DZZ -40 to 85 C Lead Free 28-pin TSSOP CDB4360 Evaluation Board
ATAPI Mixing Logic Levels Between 5.0 V and 1.8 V +3.3 V or +5 V Analog Power Supply 116 mW with 3.3 V Supply Popguard Technology(R) for Control of Clicks and Pops
I
DIF1/SCL/CCLK DIF0/SDA/CDIN M1/AD0/CS
M2
VLC
MUTEC1
MUTEC2
MUTEC3
RST
C o nt r o l P o rt
E xt e rn a l M ut e C o ntr ol V olu m e C o n t ro l Mi xe r D A C A n alo g Filt e r A O U T A1
I nt e r p o la ti o n F ilt e r VLS S C LK S e ri al P o rt L RC K SD I N1 SD I N2 SD I N3 I nt e r p o la ti o n F ilt e r M C LK I nt e r p o la ti o n F ilt e r I nt e r p o la ti o n F ilt e r
V olu m e C o nt r o l
D A C D A C
A n alo g F ilt e r
A O UT B1
I nt e r p o la ti o n F ilt e r
V olu m e C o n t ro l Mi xe r
A n alo g F ilt e r
A O U T A2
I nt e r p o la ti o n F ilt e r
V olu m e C o nt r o l
D A C D A C
A n alo g F ilt e r
A O UT B2
V olu m e C o n t ro l Mi xe r V olu m e C o nt r o l
A n alo g F ilt e r
A O U T A3
D A C
A n alo g F ilt e r
A O UT B3 VQ FILT+
/2
VD
GND GND
VA
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2004 (All Rights Reserved)
(c)
JUL `04 DS517F2 1
CS4360
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................... 5 2. TYPICAL CONNECTION DIAGRAM ...................................................................................... 7 3. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 8 SPECIFIED OPERATING CONDITIONS ................................................................................. 8 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 8 ANALOG CHARACTERISTICS (CS4360-KZ/KZZ) .................................................................. 9 ANALOG CHARACTERISTICS (CS4360-DZZ) ..................................................................... 11 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE......................... 13 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE........................................... 16 SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE ....................................... 17 SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE ....................................... 18 DC ELECTRICAL CHARACTERISTICS................................................................................. 19 DIGITAL INPUT CHARACTERISTICS ................................................................................... 19 DIGITAL INTERFACE SPECIFICATIONS.............................................................................. 20 THERMAL CHARACTERISTICS AND SPECIFICATIONS .................................................... 20 4. APPLICATIONS ...................................................................................................................... 21 4.1 Sample Rate Range/Operational Mode Select ................................................................ 21 4.1.1 Stand-alone Mode ............................................................................................... 21 4.1.2 Control Port Mode ............................................................................................... 21 4.2 System Clocking .............................................................................................................. 21 4.3 Digital Interface Format .................................................................................................... 22 4.3.1 Stand-alone Mode ............................................................................................... 22 4.3.2 Control Port Mode .............................................................................................. 23 4.4 De-emphasis Control ....................................................................................................... 23 4.4.1 Stand-alone Mode ............................................................................................... 24 4.4.2 Control Port Mode ............................................................................................... 24 4.5 Recommended Power-up Sequence ............................................................................... 24
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com/
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. IC is a registered trademark of Philips Semiconductor. Purchase of IC Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips IC Patent Rights to use those components in a standard IC system.
2
DS517F2
CS4360
4.5.1 Stand-alone Mode ............................................................................................... 24 4.5.2 Control Port Mode ............................................................................................... 24 4.6 Popguard(R) Transient Control .......................................................................................... 24 4.6.1 Power-up ............................................................................................................. 24 4.6.2 Power-down ........................................................................................................ 24 4.6.3 Discharge Time ................................................................................................... 25 4.7 Mute Control .................................................................................................................... 25 4.8 Grounding and Power Supply Arrangements .................................................................. 25 4.8.1 Capacitor Placement ........................................................................................... 25 4.8.2 Power Supply Sections ....................................................................................... 25 4.9 Control Port Interface ...................................................................................................... 25 4.9.1 Memory Address Pointer (MAP) ......................................................................... 26 4.9.1a INCR (Auto Map Increment) ................................................................ 26 4.9.1b MAP0-3 (Memory Address Pointer) ..................................................... 26 4.9.2 IC Mode ............................................................................................................. 26 4.9.2a IC Write ............................................................................................... 26 4.9.2b IC Read ............................................................................................... 27 4.9.3 SPI Mode ............................................................................................................ 27 4.9.3a SPI Write .............................................................................................. 28 5. REGISTER QUICK REFERENCE ......................................................................................... 29 6. REGISTER DESCRIPTIONS .................................................................................................. 30 6.1 Mode Control 1 (address 01h) ......................................................................................... 30 6.1.1 Auto-mute (AMUTE) Bit 7 ....................................................................................... 30 6.1.2 Digital Interface Format (DIF) Bit 4-6 ...................................................................... 30 6.1.3 De-emphasis Control (DEM) Bit 2-3........................................................................ 31 6.1.4 Functional Mode (FM) Bit 0-1.................................................................................. 31 6.2 Invert Signal (address 02h) ............................................................................................. 31 6.2.1 Invert Signal Polarity (INV_xx) Bit 0-5 ..................................................................... 31 6.3 Mixing Control Pair 1 (Channels A1 & B1) (address 03h) Mixing Control Pair 2 (Channels A2 & B2) (address 04h) Mixing Control Pair 3 (Channels A3 & B3) (address 05h)............................................. 31 6.3.1 ATAPI Channel Mixing and Muting (atapi) Bit 0-3................................................... 32 6.4 Volume Control (addresses 06h - 0Bh) ........................................................................... 33 6.4.1 MUTE (MUTE) Bit 7 ................................................................................................ 33 6.4.2 VOLUME CONTROL (xx_VOL) Bit 0-6 ................................................................... 33 6.5 Mode Control 2 (address 0Dh) ......................................................................................... 33 6.5.1 Soft Ramp and Zero Cross CONTROL (SZC) Bit 6-7 ............................................. 33 6.5.2 Control Port Enable (CPEN) Bit 5 ........................................................................... 34 6.5.3 Power Down (PDN) Bit 4......................................................................................... 34 6.5.4 Popguard(R) Transient Control (POPG) Bit 3 ........................................................... 34 6.5.5 Freeze Controls (FREEZE) Bit 2............................................................................. 35 6.5.6 Master Clock DIVIDE ENABLE (MCLKDIV) Bit 1 ................................................... 35 6.5.7 Single Volume Control (SNGLVOL) Bit 0 ................................................................ 35 6.6 Revision Register (Read Only) (address 0Dh) ................................................................ 35 6.6.1 Revision Indicator (REV) [Read Only] Bit 0-3 ......................................................... 35 7. PARAMETER DEFINITIONS .................................................................................................. 36 Total Harmonic Distortion + Noise (THD+N) .......................................................................... 36 Dynamic Range ...................................................................................................................... 36 Interchannel Isolation ............................................................................................................. 36 Interchannel Gain Mismatch ................................................................................................... 36 Gain Error ............................................................................................................................... 36 Gain Drift ................................................................................................................................ 36 DS517F2 3
CS4360
8. REFERENCES ........................................................................................................................ 36 9. PACKAGE DIMENSIONS ....................................................................................................... 37
LIST OF FIGURES
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Typical Connection Diagram .......................................................................................... 7 Output Test Load ......................................................................................................... 10 Maximum Loading ........................................................................................................ 10 Single-speed Stopband Rejection ................................................................................ 14 Single-speed Transition Band ...................................................................................... 14 Single-speed Transition Band (Detail) ......................................................................... 14 Single-speed Passband Ripple .................................................................................... 14 Double-speed Stopband Rejection .............................................................................. 14 Double-speed Transition Band ..................................................................................... 14 Double-speed Transition Band (Detail) ........................................................................ 15 Double-speed Passband Ripple ................................................................................... 15 Serial Mode Input Timing ............................................................................................. 16 Control Port Timing - IC Mode .................................................................................... 17 Control Port Timing - SPI Mode ................................................................................... 18 Left Justified up to 24-Bit Data ..................................................................................... 23 I2S, up to 24-Bit Data ................................................................................................... 23 Right Justified Data ...................................................................................................... 23 De-emphasis Curve ..................................................................................................... 23 IC Write ....................................................................................................................... 27 IC Read ....................................................................................................................... 27 SPI Write ...................................................................................................................... 28 ATAPI Block Diagram .................................................................................................. 32
LIST OF TABLES
Table 1. CS4360 Stand-alone Operational Mode............................................................................. 21 Table 2. CS4360 Control Port Operational Mode ............................................................................. 21 Table 3. Single-speed Mode Standard Frequencies ........................................................................ 21 Table 4. Double-speed Mode Standard Frequencies ....................................................................... 21 Table 5. Quad-speed Mode Standard Frequencies ......................................................................... 22 Table 6. Digital Interface Format - Stand-alone Mode...................................................................... 22 Table 7. Power Supply Control Sections .......................................................................................... 25 Table 8. Digital Interface Formats - Control Port Mode .................................................................... 30 Table 9. ATAPI Decode .................................................................................................................... 32 Table 10. Example Digital Volume Settings ..................................................................................... 33
4
DS517F2
CS4360
1. PIN DESCRIPTION
VLS SDIN1 SDIN2 SDIN3 SCLK LRCK MCLK VD GND RST DIF1/SCL/CCLK DIF0/SDA/CDIN M1/AD0/CS VLC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
MUTEC1 AOUTA1 AOUTB1 MUTEC2 AOUTA2 AOUTB2 VA GND AOUTA3 AOUTB3 MUTEC3 VQ FILT+ M2
CS4360
22 21 20 19 18 17 16 15
DS517F2
5
CS4360
Pin Name
VLS SDIN1 SDIN2 SDIN3 SCLK LRCK MCLK VD GND RST VLC FILT+ VQ VA AOUTB3 AOUTA3 AOUTB2 AOUTA2 AOUTB1 AOUTA1 MUTEC3 MUTEC2 MUTEC1 Control Port Definitions SCL/CCLK SDA/CDIN AD0/CS Stand-Alone Definitions DIF1 DIF0 M1 M2
# 1 2 3 4 5 6 7 8 9 21 10 14 16 17 22 19 20 23 24 26 27 18 25 28
Pin Description
Serial Audio Interface Power (Input) - Positive power for the serial audio interface. Serial Audio Data Input (Input) - Input for two's complement serial audio data.
Serial Clock (Input) - Serial clock for the serial audio interface. Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Digital Power (Input) - Positive power supply for the digital section. Ground (Input) Reset (Input) - Powers down device and resets all internal resisters to their default settings. Control Port Interface Power (Input) - Positive power for the control port interface. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. Analog Power (Input) - Positive power supply for the analog section. Analog Outputs (Output) - The full scale analog line output level is specified in the Analog Characteristics and Specifications table.
Mute Control (Output) - Control signal for optional mute circuit.
11 12 13
Serial Control Port Clock (Input) - Serial clock for the control port interface. Serial Control Data I/O (Input/Output) - Input/Output for IC data. Input for SPI data. Address Bit / Chip Select (Input) - Chip address bit in IC Mode. Control signal used to select the chip in SPI mode.
11 12 13 15
Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial Clock and Serial Audio Data. Mode Selection (Input) - Determines the operational mode of the device.
6
DS517F2
CS4360
2. TYPICAL CONNECTION DIAGRAM
+3.3 V to +5 V * 1 F + 0.1 F 22 VA 8 VD AOUTA1 27 + 3.3 F 0.1 F + 1 F
+3.3 V to VA *
* All supplies can be tied together 560 AOUTA1 10 k 560 C OPTIONAL MUTE CIRCUIT 10 k C AOUTB1 RL RL
7 6 Digital Audio Source 5 4 3 2
MCLK LRCK SCLK SDIN1 SDIN2 SDIN3
AOUTB1
26 + 3.3 F 28 24 + 3.3 F
MUTEC1 AOUTA2
560 AOUTA2 10 k 560 C OPTIONAL MUTE CIRCUIT 10 k C AOUTB2 RL RL
+1.8 V to +5 V *
1 0.1 F
VLS
AOUTB2
23 + 3.3 F 25 20 + 3.3 F
CS4360
MUTEC2 560
10 11 C/ Mode Configuration 12 13 15
RST DIF1/SCL/CCLK DIF0/SDA/CDIN M1/AD0/CS M2
AOUTA3
AOUTA3 10 k 560 C OPTIONAL MUTE CIRCUIT AOUTB3 RL RL
AOUTB3
19 + 3.3 F 18
10 k
C
+1.8 V to +5 V *
14 0.1 F
VLC
MUTEC3
FILT+ 16 VQ 17 0.1 F + 3.3 F 0.1 F + 3.3 F
GND 9
GND 21 C=
R L+560 4 Fs(R L 560)
Figure 1. Typical Connection Diagram
DS517F2
7
CS4360
3. CHARACTERISTICS AND SPECIFICATIONS
Typical performance characteristics are derived from measurements taken at TA = 25C. Min/Max performance characteristics and specifications are guaranteed over the operating temperature and voltages.
SPECIFIED OPERATING CONDITIONS
Parameters DC Power Supply Analog
(Note 1)
GND = 0 V; all voltages with respect to GND. Symbol Min 3.0 4.5 2.25 3.0 4.5 1.7 2.25 3.0 4.5 1.7 2.25 3.0 4.5 Typ 3.3 5 2.5 3.3 5 1.8 2.5 3.3 5 1.8 2.5 3.3 5 Max 3.6 5.5 2.75 3.6 5.5 1.9 2.75 3.6 5.5 1.9 2.75 3.6 5.5 Units V V V V V V V V V V V V V
Digital
(Note 1)
Serial Audio Interface
Control Port Interface
3.3 V 5.0 V 2.5 V 3.3 V 5.0 V 1.8 V 2.5 V 3.3 V 5.0 V 1.8 V 2.5 V 3.3 V 5.0 V
Nominal Nominal Nominal Nominal Nominal Nominal Nominal Nominal Nominal Nominal Nominal Nominal Nominal
VA VD
VLS
VLC
ABSOLUTE MAXIMUM RATINGS
GND = 0 V; all voltages with respect to GND. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameters DC Power Supply Analog Digital Serial Audio Interface Control Port Interface
(Note 2)
Symbol VA VD VLS VLC Iin VIND_S VIND_C TA Tstg
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 -65
Max 6.0 6.0 6.0 6.0 10 VLS+0.4 VLC+0.4 125 150
Units V V V V mA V V C C
Input Current Digital Input Voltage
Serial Audio Interface Control Port Interface
Ambient Operating Temperature (power applied) Storage Temperature
Notes: 1. Nominal VD supply must be less than or equal to the nominal VA supply. 2. Any pin except supplies.
8
DS517F2
CS4360
ANALOG CHARACTERISTICS (CS4360-KZ/KZZ)
Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load RL = 10 k, C L = 10 pF (see Figure 2). All supplies = VA = 5.0 V or 3.3 V. 5.0 V Parameter Single-Speed Mode Dynamic Range Fs = 48 kHz
(Note 3)
3.3 V Max Min Typ Max Unit
Min
Typ
unweighted A-Weighted A-Weighted Total Harmonic Distortion + Noise
(Note 3)
94 97 -
99 102 100 -91 -79 -39
-86 -
89 92 -
94 97 97 -91 -74 -34
-86 -
dB dB dB dB dB dB
0 dB -20 dB -60 dB Double-Speed Mode Dynamic Range Fs = 96 kHz
(Note 3)
40 kHz Bandwidth Total Harmonic Distortion + Noise
unweighted A-Weighted A-Weighted
(Note 3)
94 97 -
99 102 100 -91 -79 -39
-86 -
89 92 -
94 97 97 -91 -74 -34
-86 -
dB dB dB dB dB dB
0 dB -20 dB -60 dB Quad-Speed Mode Dynamic Range Fs = 192 kHz
(Note 3)
40 kHz Bandwidth Total Harmonic Distortion + Noise
unweighted A-Weighted A-Weighted
(Note 3)
94 97 -
99 102 100 -91 -79 -39
-86 -
89 92 -
94 97 97 -91 -74 -34
-86 -
dB dB dB dB dB dB
0 dB -20 dB -60 dB
Notes: 3. One-half LSB of triangular PDF dither is added to data.
DS517F2
9
CS4360
ANALOG CHARACTERISTICS (CS4360-KZ/KZZ) (Continued)
Parameters Dynamic Performance for All Modes Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Characteristics and Specifications Full Scale Output Voltage Output Impedance Minimum AC-Load Resistance Maximum Load Capacitance 4. Refer to Figure 3.
(Note 4) (Note 4)
Symbol (1 kHz) ICGM
Min -
Typ 102 0.1 100
Max -
Units dB dB ppm/C Vpp k pF
0.60*VA 0.66*VA 0.72*VA Zout RL CL 100 3 100 -
.
125 Capacitive Load -- C L (pF) 100 75 50 25 Safe Operating Region
3.3 F AOUTx + V out R L C L
AGND
2.5 3
5
10
15
20
Resistive Load -- RL (k )
Figure 2. Output Test Load
Figure 3. Maximum Loading
10
DS517F2
CS4360
ANALOG CHARACTERISTICS (CS4360-DZZ)
Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load R L = 10 k, CL = 10 pF (see Figure 2). All supplies = VA = 5.0 V and 3.3 V. VA = 5.0 V Parameter Single-speed Mode Dynamic Range Fs = 48 kHz
(Note 3)
VA = 3.3 V Max Min Typ Max Unit
Min
Typ
unweighted A-Weighted A-Weighted Total Harmonic Distortion + Noise
(Note 3)
89 92 -
99 102 100 -91 -79 -39
-84 -
89 92 -
94 97 97 -91 -74 -34
-84 -
dB dB dB dB dB dB
0 dB -20 dB -60 dB Double-speed Mode Dynamic Range Fs = 96 kHz
(Note 3)
40 kHz Bandwidth Total Harmonic Distortion + Noise
unweighted A-Weighted A-Weighted
(Note 3)
89 92 -
99 102 100 -91 -79 -39
-84 -
89 92 -
94 97 97 -91 -74 -34
-84 -
dB dB dB dB dB dB
0 dB -20 dB -60 dB Quad-speed Mode Dynamic Range Fs = 192 kHz
(Note 3)
40 kHz Bandwidth Total Harmonic Distortion + Noise
unweighted A-Weighted A-Weighted
(Note 3)
89 92 -
99 102 100 -91 -79 -39
-84 -
89 92 -
94 97 97 -91 -74 -34
-84 -
dB dB dB dB dB dB
0 dB -20 dB -60 dB
DS517F2
11
CS4360
ANALOG CHARACTERISTICS (CS4360-DZZ) (Continued)
Parameters Dynamic Performance for All Modes Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Characteristics and Specifications Full Scale Output Voltage Output Impedance AC-load Resistance Load Capacitance
(Note 4) (Note 4)
Symbol (1 kHz) ICGM
Min -
Typ 102 0.1 100
Max -
Units dB dB ppm/C Vpp k pF
0.60*VA 0.66*VA 0.72*VA Zout RL CL 3 100 100
12
DS517F2
CS4360
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
The filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Parameter Single-Speed Mode (4 kHz to 50 kHz sample rates) Passband to -0.05 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay De-emphasis Error (Relative to 1 kHz) Control Port Mode
(Note 6) (Note 5)
Min
Typ
Max
Unit
0 0 -0.02 0.5465 50 -
9/Fs -
0.4535 0.4998 +0.035 +0.2/-0.1 +0.05/-0.14 +0/-0.22 +1.5/-0 +0.05/-0.14 +0.2/-0.4
Fs Fs dB Fs dB s dB dB dB dB dB dB
Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz
-
Stand-alone Mode
Double-Speed Mode (50 kHz to 100 kHz sample rates) Passband to -0.1 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Quad-Speed Mode - (100 kHz to 200 kHz sample rates) Passband to -3 dB corner Frequency Response 10 Hz to 20 kHz Group Delay 0 -0.7 1.5/Fs 0.25 0 Fs dB s
(Note 5)
0 0 -0.1 0.577 55 -
4/Fs
0.4621 0.4982 0 -
Fs Fs dB Fs dB s
Notes: 5. For Single-speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For Double-speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs. 6. De-emphasis is only available in Single-speed Mode.
DS517F2
13
CS4360
Figure 4. Single-speed Stopband Rejection
Figure 5. Single-speed Transition Band
Figure 6. Single-speed Transition Band (Detail)
Figure 7. Single-speed Passband Ripple
Figure 8. Double-speed Stopband Rejection
Figure 9. Double-speed Transition Band
14
DS517F2
CS4360
Figure 10. Double-speed Transition Band (Detail)
Figure 11. Double-speed Passband Ripple
DS517F2
15
CS4360
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Inputs: Logic 0 = GND, Logic 1 = VLS. Parameters MCLK Frequency MCLK Duty Cycle Input Sample Rate Single-speed Mode Double-speed Mode Quad-speed Mode Fs Fs Fs tsclkl tsclkh Single-speed Mode Double-speed Mode Quad-speed Mode (MCLKDIV = 0) Quad-speed Mode (MCLKDIV = 1) SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDINx valid to SCLK rising setup time SCLK rising to SDINx hold time tslrd tslrs tsdlrs tsdh Symbol Min 1.024 40 4 50 100 45 20 20 20 20 20 20 Max 51.2 60 50 100 200 55 128xFs 64xFs
MCLK ----------------2 MCLK ----------------4
Units MHz % kHz kHz kHz % ns ns Hz Hz Hz Hz ns ns ns ns
LRCK Duty Cycle SCLK Pulse Width Low SCLK Pulse Width High SCLK Frequency
-
LRCK
t t s lrd
s lrs t s c lk l
t
s c lk h
SCLK
t
t s d lrs
sdh
S D IN x
Figure 12. Serial Mode Input Timing
16
DS517F2
CS4360
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE
Inputs: Logic 0 = GND, Logic 1 = VLC Parameter IC Mode SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling
(Note 8) (Note 7)
Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc, trc tfc, tfc tsusp tack
Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 -
Max 100 1 300 (Note 9)
Unit kHz ns s s s s s s ns s ns s ns
Notes: 7. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 8. The acknowledge delay is based on MCLK and can limit the maximum transaction speed. 9.
5 5 5 -------------------- for Single-Speed Mode, -------------------- for Double-Speed Mode, ----------------- for Quad-Speed Mode. 256 x Fs 128 x Fs 64 x Fs
RST t S to p irs S t a rt R e p e a te d S t a rt t rd t fd S to p
SDA t b uf t h dst t high t h d st t fc t susp
SCL t t t su d t a ck t su st t rc
lo w
hd d
Figure 13. Control Port Timing - IC Mode
DS517F2
17
CS4360
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE
Parameter SPI Mode CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN
(Note 11) (Note 12) (Note 12) (Note 10)
(Continued) Max 6 100 100 Unit MHz ns ns s ns ns ns ns ns ns ns
Symbol fsclk tsrs tspi tcsh tcss tscl tsch tdsu tdh tr2 tf2
Min 500 500 1.0 20
1 ----------------MCLK 1 ----------------MCLK
40 15 -
Notes: 10. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 11. Data must be held for sufficient time to bridge the transition time of CCLK. 12. For fsclk < 1 MHz.
RST
t srs
CS t sp i t css C C LK t r2
C D IN
t scl
t sch
t csh
t f2
t dsu t dh
Figure 14. Control Port Timing - SPI Mode
18
DS517F2
CS4360
DC ELECTRICAL CHARACTERISTICS
Parameters Normal Operation (Note 13) Power Supply Current VA = 5.0 V VD = 5.0 V VA = 3.3 V VD = 3.3 V VLS = 5.0 V VLC = 5.0 V VLS = 3.3 V VLC = 3.3 V
(Note 14)
GND = 0 V; all voltages with respect to GND. Symbol IA ID IA ID ILS ILC ILS ILC Min PSRR Typ 22 25 21 14 6 2 2 1 235 116 16 12 80 40 60 40 0.5*VA 250 0.01 VA 250 0.01 0 VA 3 Max 265 128 Units mA mA mA mA A A A A mW mW A A W W dB dB V
Power Dissipation Power-down Mode (Note 15) Power Supply Current Power Dissipation All Modes of Operation Power Supply Rejection Ratio (Note 16)
All Supplies = 5.0 V All Supplies = 3.3 V All Supplies = 5.0 V All Supplies = 3.3 V All Supplies = 5.0 V All Supplies = 3.3 V 1 kHz 60 Hz
VQ Nominal Voltage Output Impedance Maximum allowable DC current source/sink Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink MUTEC Low-level Output Voltage MUTEC High-level Output Voltage Maximum MUTEC Drive Current
k
mA V
k
mA V V mA
Notes: 13. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input sampled at the highest Fs for each speed mode, and open outputs, unless otherwise specified. 14. ILC measured with no external loading on pin 12 (SDA). 15. Power Down Mode is defined as RST = LO with all clocks and data lines held static. 16. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 1. Increasing the capacitance will also increase the PSRR.
DIGITAL INPUT CHARACTERISTICS
Parameters Input Leakage Current Input Capacitance
GND = 0 V; all voltages with respect to GND. Symbol Iin Min Typ 8 Max 10 Units A pF
DS517F2
19
CS4360
DIGITAL INTERFACE SPECIFICATIONS
Parameters 1.8 V Logic High-level Input Voltage Low-level Input Voltage 2.5 V Logic High-level Input Voltage Low-level Input Voltage 3.3 V Logic High-level Input Voltage Low-level Input Voltage 5.0 V Logic High-level Input Voltage Low-level Input Voltage Serial Audio Control Port Serial Audio Control Port VIH VIH VIL VIL 70% 70% 13% 13% VLS VLC VLS VLC Serial Audio Control Port Serial Audio Control Port VIH VIH VIL VIL 70% 70% 13% 13% VLS VLC VLS VLC Serial Audio Control Port Serial Audio Control Port VIH VIH VIL VIL 70% 70% 13% 13% VLS VLC VLS VLC Serial Audio Control Port Serial Audio Control Port VIH VIH VIL VIL 80% 80% 13% 13% VLS VLC VLS VLC GND = 0 V; all voltages with respect to GND. Symbol Min Max Units
THERMAL CHARACTERISTICS AND SPECIFICATIONS
Parameters Package Thermal Resistance TSSOP (-KZ/KZZ & -DZZ) -KZ/KZZ -DZZ Ambient Operating Temperature (Power Applied) Symbol JA TA Min -10 -40 Typ 40 Max +70 +85 Units C/Watt C C
20
DS517F2
CS4360
4. APPLICATIONS 4.1 4.1.1 Sample Rate Range/Operational Mode Select Stand-Alone Mode
The device operates in one of four operational modes determined by the Mode pins in Stand-alone mode. Sample rates outside the specified range for each mode are not supported.
M2 0 0 1 1 M1 0 1 0 1 Input Sample Rate (FS) 4 kHz - 50 kHz 32 kHz - 48 kHz 50 kHz - 100 kHz 100 kHz - 200 kHz MODE Single-Speed (without De-emphasis) Single-Speed (with De-emphasis) Double-Speed Quad-Speed
Table 1. CS4360 Stand-Alone Operational Mode
4.1.2
Control Port Mode
The device operates in one of three operational modes determined by the FM bits (see section 6.1.4) in Control Port mode. Sample rates outside the specified range for each mode are not supported.
FM1 0 0 1 1
FM0 0 1 0 1
Input Sample Rate (FS) 4 kHz - 50 kHz 50 kHz - 100 kHz 100 kHz - 200 kHz Reserved Single-speed Double-speed Quad-speed Reserved
MODE
Table 2. CS4360 Control Port Operational Mode
4.2
System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks. The LRCK, defined also as the input sample rate (Fs), must be synchronously derived from the MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 3-5.
Sample Rate (kHz) 32 44.1 48 MCLK (MHz) 512x 16.3840 22.5792 24.5760
256x 8.1920 11.2896 12.2880
384x 12.2880 16.9344 18.4320
768x 24.5760 33.8688 36.8640
1024x* 32.7680 45.1584 49.1520
Table 3. Single-speed Mode Standard Frequencies
Sample Rate (kHz) 64 88.2 96
128x 8.1920 11.2896 12.2880
192x 12.2880 16.9344 18.4320
MCLK (MHz) 256x 16.3840 22.5792 24.5760
384x 24.5760 33.8688 36.8640
512x* 32.7680 45.1584 49.1520
Table 4. Double-speed Mode Standard Frequencies
DS517F2
21
CS4360
Sample Rate (kHz) 176.4 192
64x 11.2896 12.2880
96x 16.9344 18.4320
MCLK (MHz) 128x 22.5792 24.5760
192x 33.8688 36.8640
256x* 45.1584 49.1520
Table 5. Quad-speed Mode Standard Frequencies
*Requires MCLKDIV bit = 1 in the Mode Control 2 register (address 0Ch)
4.3
Digital Interface Format
The device will accept audio samples in 1 of 4 digital interface formats in Stand-alone mode, as illustrated in Table 6, and 1 of 6 formats in Control Port mode, as illustrated in Table 8.
4.3.1
Stand-Alone Mode
The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship between the LRCK, SCLK and SDIN, see Figures 15-17.
DIF1 0 0 1 1 DIF0 0 1 0 1 DESCRIPTION
Left Justified, up to 24-bit Data I2S, up to 24-bit Data Right Justified, 16-bit Data Right Justified, 24-bit Data
Table 6. Digital Interface Format - Stand-alone Mode
FORMAT 0 1 2 3
FIGURE 16 15 17 17
22
DS517F2
CS4360
4.3.2 Control Port Mode
The desired format is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control 2 register (see section 6.1.2). For an illustration of the required relationship between LRCK, SCLK and SDIN, see Figures 15-17.
LRC K
L e ft C ha n n el
R ig ht C h a n n el
S CLK
S D IN
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LS B
M SB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LS B
Figure 15. Left Justified up to 24-Bit Data
LRC K
L e ft C ha n n el
R ig ht C h a n n el
S CLK
S D IN
M SB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 16. I2S, up to 24-Bit Data
L RC K
L e ft C ha n ne l
R ig h t C ha nn e l
SC LK
SDIN
LS B
MSB
-1 -2 -3 -4 -5
+7 +6 +5 +4 +3 +2 +1
LS B
MSB
-1 -2 -3 -4 -5
+7 +6 +5 +4 +3 +2 +1
LSB
Figure 17. Right Justified Data
4.4
De-Emphasis Control
The device includes on-chip digital de-emphasis. Figure 18 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs.
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 18. De-emphasis Curve
Notes: De-emphasis is only available in Single-speed Mode. DS517F2 23
CS4360
4.4.1 Stand-Alone Mode
The operational mode pins, M2 and M1, selects the 44.1 kHz de-emphasis filter. Please see section 4.1 for the desired de-emphasis control.
4.4.2
Control Port Mode
The Mode Control bits selects either the 32, 44.1, or 48 kHz de-emphasis filter. Please see section 6.1.3 for the desired de-emphasis control.
4.5 4.5.1
Recommended Power-up Sequence Stand-Alone Mode
1) Hold RST low until the power supply and configuration pins are stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 4.2. In this state, the control port is reset to its default settings and VQ will remain low. 2) Bring RST high. The device will remain in a low power state with VQ low and will initiate the Standalone power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
4.5.2
Control Port Mode
1) Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 4.2. In this state, the control port is reset to its default settings and VQ will remain low. 2) Bring RST high. The device will remain in a low power state with VQ low. 3) Load the desired register settings while keeping the PDN bit set to 1. 4) Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 S when the POPG bit is set to 0. If the POPG bit is set to 1, see Section 4.6 for a complete description of power-up timing.
4.6
Popguard(R) Transient Control
The CS4360 uses a novel technique to minimize the effects of output transients during power-up and power-down. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated inside the DAC when the RST pin or PDN bit is enabled/disabled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors.
4.6.1
Power-up
When the device is initially powered-up, the audio outputs, AOUTAx and AOUTBx, are clamped to GND. Following a delay of approximately 1000 LRCK cycles, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing the power-up transient.
4.6.2
Power-down
To prevent transients at power-down, the device must first enter its power-down state. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTAx and AOUTBx. In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on.
24
DS517F2
CS4360
4.6.3 Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning on the power or exiting the power-down state. If full discharge does not occur, a transient will occur when the audio outputs are initially clamped to GND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance and the output load. For example, with a 3.3 F capacitor, the minimum power-down time will be approximately 0.4 seconds.
4.7
Mute Control
The Mute Control pins go high during power-up initialization, reset, muting (see section 6.1.1 and 6.4.1), or if the MCLK to LRCK ratio is incorrect. These pins are intended to be used as control for external mute circuits to prevent the clicks and pops that can occur in any single-ended single supply system. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. Please see the CDB4360 data sheet for a suggested mute circuit.
4.8
Grounding and Power Supply Arrangements
As with any high-resolution converter, the CS4360 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA, VD, VLS and VLC connected to clean supplies. If the ground planes are split between digital ground and analog ground, the GND pins of the CS4360 should be connected to the analog ground plane. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The CDB4360 evaluation board demonstrates the optimum layout and power supply arrangements.
4.8.1
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low-value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin and referenced to analog ground.
4.8.2
Power Supply Sections
Each power supply pin provides power to specific sections of the CS4360. The logic voltage level for each section must adhere to the corresponding power supply voltage setting. For example: If VLC = 1.8 V; VLS = 3.3 V; VD = VA = 5 V; then the logic level for all mode configuration inputs must equal 1.8 V.
Pin #s 2, 3, 4, 5, 6, 7 10, 11, 12, 13, 15 Description
Serial Audio Interface Inputs Mode Configuration Inputs
Table 7. Power Supply Control Sections
Power Supply Reference VLS VLC
4.9
Control Port Interface
The control port is used to load all the internal register settings (see section 6). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates in one of two modes: IC or SPI.
Notes: MCLK must be applied during all IC communication.
DS517F2
25
CS4360
4.9.1 Memory Address Pointer (MAP)
The MAP byte precedes the control port register byte during a write operation and is not available again until after a start condition is initiated. During a read operation the byte transmitted after the ACK will contain the data of the register pointed to by the MAP (see sections 4.9.1a and 4.9.3 for write/read details).
7 INCR 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 MAP3 0 2 MAP2 0 1 MAP1 0 0 MAP0 0
4.9.1a
INCR (Auto Map Increment)
The device has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive IC writes or reads and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers.
Default = `0' 0 - Disabled 1 - Enabled
4.9.1b 4.9.2
MAP0-3 (Memory Address Pointer)
Default = `0000'
IC Mode
In the IC mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial control port clock, SCL. There is no CS pin. Pin AD0 enables the user to alter the chip address (001000[AD0][R/W]) and should be tied to VLC or GND as required, before powering up the device. If the device ever detects a high-to-low transition on the AD0/CS pin after power-up, SPI mode will be selected.
4.9.2a
IC Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifications in section 3. 1) Initiate a START condition to the IC bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth bit of the address byte is the R/W bit. 2) Wait for an acknowledge (ACK) from the device, then write to the memory address pointer, MAP. This byte points to the register to be written. 3) Wait for an acknowledge (ACK) from the device, then write the desired data to the register pointed to by the MAP. 4) If the INCR bit (see section 4.9.1a) is set to 1, repeat the previous step until all the desired registers are written, then initiate a STOP condition to the bus. 5) If the INCR bit is set to 0 and further IC writes to other registers are desired, it is necessary to repeat the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP condition to the bus.
26
DS517F2
CS4360
SDA
0 01 00 0
AD0
W
ACK
M AP 1 -8
ACK
D A TA 1-8
ACK
SCL S top
S ta rt
Figure 19. IC Write
4.9.2b
IC Read
To read from the device, follow the procedure below while adhering to the control port Switching Specifications. During this operation it is first necessary to write to the device, specifying the appropriate register through the MAP. 1) After writing to the MAP (see section 4.9.1), initiate a repeated START condition to the IC bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte is the R/W bit. 2) Signal the end of the address byte by not issuing an acknowledge. The device will then transmit the contents of the register pointed to by the MAP. The MAP will contain the address of the last register written to the MAP. 3) If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Continue providing a clock but do not issue an ACK on the bytes clocked out of the device. After all the desired registers are read, initiate a STOP condition to the bus. 4) If the INCR bit is set to 0 and further IC reads from other registers are desired, it is necessary to repeat the procedure detailed from step 1. If no further reads from other registers are desired, initiate a STOP condition to the bus.
SDA
0 01 00 0
AD 0
W
ACK
M AP 1-8
ACK
0 01 00 0
AD0
R
AC K
D a ta 1 -8
(po in te d to b y M A P )
ACK
D a ta 1 -8
(p oin te d to b y M A P )
SC L R ep e a te d S T A R T or A b o rte d W R IT E
S ta rt
S to p
Figure 20. IC Read
4.9.3
SPI Mode
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK (see Figure 21 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and is used to control SPI writes to the control port. When the device detects a high-to-low transition on the AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the rising edge of CCLK.
DS517F2
27
CS4360
4.9.3a SPI Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifications in section 3. 1) Bring CS low. 2) The address byte on the CDIN pin must then be 00100000. 3) Write to the memory address pointer, MAP. This byte points to the register to be written. 4) Write the desired data to the register pointed to by the MAP. 5) If the INCR bit (see section 4.9.1a) is set to 1, repeat the previous step until all the desired registers are written, then bring CS high. 6) If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring CS high, and repeat the procedure detailed from step 1. If no further writes to other registers are desired, bring CS high.
CS CCLK C H IP ADDRESS C D IN
00 10 0 00
R/W
MAP
MSB
DATA
LS B
by te 1 M A P = M e m o ry Ad dre s s P o in te r
b yte n
Figure 21. SPI Write
28
DS517F2
CS4360
5.
1h 2h 3h 4h 5h 6h 7h 8h 9h 0Ah 0Bh 0Ch 0Dh
REGISTER QUICK REFERENCE
Function
Mode Control 1 default Invert Signal default Mixing Control P1 default Mixing Control P2 default Mixing Control P3 default Volume Control A1 default Volume Control B1 default Volume Control A2 default Volume Control B2 default Volume Control A3 default Volume Control B3 default Mode Control 2 default Revision Indicator default
Addr
7
AMUTE 1 Reserved 0 Reserved 0 Reserved 0 Reserved 0 0 0 0 0 0 0 SZC1 1 Reserved 0
6
DIF2 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 0 0 0 0 0 0 SZC0 0 Reserved 0
5
DIF1 0 INV_B3 0 Reserved 0 Reserved 0 Reserved 0 0 0 0 0 0 0 CPEN 0 Reserved 0
4
DIF0 0 INV_A3 0 0 0 0 0 0 0 0 0 0 PDN 1 Reserved 0
3
DEM1 0 INV_B2 0 1 1 1 A1_VOL3 0 B1_VOL3 0 A2_VOL3 0 B2_VOL3 0 A3_VOL3 0 B3_VOL3 0 POPG 1 REV3 X
2
DEM0 0 INV_A2 0 0 0 0 0 0 0 0 0 0 FREEZE 0 REV2 X
1
FM1 0 INV_B1 0 0 0 0 0 0 0 0 0 0 0 REV1 X
0
FM0 0 INV_A1 0 1 1 1 A1_VOL0 0 B1_VOL0 0 A2_VOL0 0 B2_VOL0 0 A3_VOL0 0 B3_VOL0 0 0 REV0 X
Reserved P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0 Reserved P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0 Reserved P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0 A1_VOL2 A1_VOL1 B1_VOL2 B1_VOL1 A2_VOL2 A2_VOL1 B2_VOL2 B2_VOL1 A3_VOL2 A3_VOL1 B3_VOL2 B3_VOL1
A1_MUTE A1_VOL6 B1_MUTE B1_VOL6 A2_MUTE A2_VOL6 B2_MUTE B2_VOL6 A3_MUTE A3_VOL6 B3_MUTE B3_VOL6
A1_VOL5 A1_VOL4 B1_VOL5 B1_VOL4 A2_VOL5 A2_VOL4 B2_VOL5 B2_VOL4 A3_VOL5 A3_VOL4 B3_VOL5 B3_VOL4
MCLKDIV SNGLVOL
DS517F2
29
CS4360
6. REGISTER DESCRIPTIONS
Note: All registers are read/write in IC mode and write only in SPI, unless otherwise stated.
6.1
MODE CONTROL 1 (ADDRESS 01H)
6 DIF2 0 5 DIF1 0
BIT 7
7 AMUTE 1
4 DIF0 0
3 DEM1 0
2 DEM0 0
1 FM1 0
0 FM0 0
6.1.1
AUTO-MUTE (AMUTE) Default = 1 0 - Disabled 1 - Enabled
Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or 1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will become active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits in the Power and Muting Control register. 6.1.2 DIGITAL INTERFACE FORMAT (DIF) BIT 4-6 Default = 000 - Format 0 (Left Justified, up to 24-bit data)
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 15-17.
DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIF0 0 1 0 1 0 1 0 1 DESCRIPTION Format 0 1 2 3 4 5 FIGURE 15 16 17 17 17 17 -
Left Justified, up to 24-bit data I2S, up to 24-bit data Right Justified, 16-bit data Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 18-bit data Reserved Reserved
Table 8. Digital Interface Formats - Control Port Mode
30
DS517F2
CS4360
6.1.3 DE-EMPHASIS CONTROL (DEM) BIT 2-3 Default = 00 00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz
Function:
Selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter response at 32-, 44.1- or 48-kHz sample rates. (See Figure 18.) Note: 6.1.4 De-emphasis is only available in Single-speed Mode.
FUNCTIONAL MODE (FM) BIT 0-1 Default = 00 00 - Single-speed Mode (4- to 50-kHz sample rates) 01 - Double-speed Mode (50- to 100-kHz sample rates) 10 - Quad-speed Mode (100- to 200-kHz sample rates) 11 - Reserved
Function:
Selects the required range of input sample rates.
6.2
INVERT SIGNAL (ADDRESS 02H)
6 Reserved 0 5 INV_B3 0 4 INV_A3 0
BIT 0-5
7 Reserved 0
3 INV_B2 0
2 INV_A2 0
1 INV_B1 0
0 INV_A1 0
6.2.1
INVERT SIGNAL POLARITY (INV_XX) Default = 0 0 - Disabled 1 - Enabled
Function:
When enabled, these bits invert the signal polarity for each of their respective channels.
6.3
MIXING CONTROL PAIR 1 (CHANNELS A1 & B1) (ADDRESS 03H) MIXING CONTROL PAIR 2 (CHANNELS A2 & B2) (ADDRESS 04H) MIXING CONTROL PAIR 3 (CHANNELS A3 & B3) (ADDRESS 05H)
6 Reserved 0 5 Reserved 0 4 Reserved 0 3 PxATAPI3 1 2 PxATAPI2 0 1 PxATAPI1 0 0 PxATAPI0 1
7 Reserved 0
DS517F2
31
CS4360
6.3.1 ATAPI CHANNEL MIXING AND MUTING (ATAPI) BIT 0-3 Default = 1001 - AOUTAx = L, AOUTBx = R (Stereo)
Function:
The CS4360 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 9 and Figure 22 for additional information. Note: All mixing functions occur prior to the digital volume control. Mixing only occurs in channel pairs.
ATAPI2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ATAPI1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ATAPI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 AOUTAx MUTE MUTE MUTE MUTE R R R R L L L L [(L+R)/2] [(L+R)/2] [(L+R)/2] [(L+R)/2] AOUTBx MUTE R L [(L+R)/2] MUTE R L [(L+R)/2] MUTE R L [(L+R)/2] MUTE R L [(L+R)/2]
ATAPI3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Table 9. ATAPI Decode
Left Channel Audio Data
A Channel Volume Control & Mute
AoutA
Right Channel Audio Data
B Channel Volume Control & Mute
AoutB
Figure 22. ATAPI Block Diagram
32
DS517F2
CS4360
6.4 VOLUME CONTROL (ADDRESSES 06H - 0BH)
6 xx_VOL6 0 5 xx_VOL5 0
BIT 7
7 xx_MUTE 0
4 xx_VOL4 0
3 xx_VOL3 0
2 xx_VOL2 0
1 xx_VOL1 0
0 xx_VOL0 0
6.4.1
MUTE (MUTE) Default = 0 0 - Disabled 1 - Enabled
Function:
The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will be retained. The muting function is affected, similar to attenuation changes, by the Soft and Zero Cross bits. The MUTEC pin will become active during the mute period if the Mute function is enabled for both channels in the pair. 6.4.2 VOLUME CONTROL (XX_VOL) BIT 0-6 Default = 0
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1-dB increments from 0 to -119 dB. Volume settings are decoded as shown in Table 10. The volume changes are implemented as dictated by the Soft Ramp and Zero Cross bits. All volume settings less than -119 dB are equivalent to enabling the MUTE bit.
Binary Code 0001010 0010100 0101000 0111100 1011010 Decimal Value 10 20 40 60 90 Volume Setting -10 dB -20 dB -40 dB -60 dB -90 dB
Table 10. Example Digital Volume Settings
6.5
MODE CONTROL 2 (ADDRESS 0DH)
7 SZC1 1 6 SZC0 0 5 CPEN 0 4 PDN 1 3 POPG 1 2 FREEZE 0 1 MCLKDIV 0 0 SNGLVOL 0
6.5.1
SOFT RAMP AND ZERO CROSS CONTROL (SZC) BIT 6-7 Default = 10 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp and Zero Cross
Function:
Immediate Change When Immediate Change is selected all level changes will be implemented immediately in one step.
DS517F2
33
CS4360
Zero Cross Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp and Zero Cross Soft Ramp and Zero Cross dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and will be implemented on successive signal zero crossings. The 1/8 dB level changes will occur after timeout periods between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter zero crossings. The zero cross function is independently monitored and implemented for each channel. 6.5.2 CONTROL PORT ENABLE (CPEN) Default = 0 0 - Disabled 1 - Enabled
BIT 5
Function:
The Control Port will become active and reset to the default settings when this function is enabled. 6.5.3 POWER DOWN (PDN) BIT 4 Default = 1 0 - Disabled 1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, but the contents of the control registers will be retained in this mode. The power-down bit defaults to `enabled' on power-up and must be disabled before normal operation in Control Port mode can occur. 6.5.4 POPGUARD(R) TRANSIENT CONTROL (POPG) BIT 3 Default = 1 0 - Disabled 1 - Enabled
Function:
The PopGuard(R) Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to the quiescent voltage during power-on or power-off when this function is enabled. Please see section 4.6 for implementation details.
34
DS517F2
CS4360
6.5.5 FREEZE CONTROLS (FREEZE) Default = 0 0 - Disabled 1 - Enabled
BIT 2
Function:
This function allows modifications to be made to the registers without the changes taking effect until the FREEZE is disabled. To have multiple changes in the control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. 6.5.6 MASTER CLOCK DIVIDE ENABLE (MCLKDIV) BIT 1 Default = 0 0 - Disabled 1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry. 6.5.7 SINGLE VOLUME CONTROL (SNGLVOL) Default = 0 0 - Disabled 1 - Enabled
BIT 0
Function:
The individual channel volume levels are independently controlled by their respective Volume Control Bytes when this function is disabled. When enabled, the volume on all channels is determined by the A1 Channel Volume Control Byte, and the other Volume Control Bytes are ignored.
6.6
REVISION REGISTER (READ ONLY) (ADDRESS 0DH)
6 Reserved 0 5 Reserved 0 4 Reserved 0 3 REV3 X 2 REV2 X 1 REV1 X 0 REV0 X
7 Reserved 0
6.6.1
REVISION INDICATOR (REV) [READ ONLY] BIT 0-3 Default = none 0001 - Revision A 0010 - Revision B 0011 - Revision C etc.
Function:
This read-only register indicates the revision level of the device.
DS517F2
35
CS4360
7. PARAMETER DEFINITIONS
The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C.
Total Harmonic Distortion + Noise (THD+N)
8.
REFERENCES
1) CDB4360 Evaluation Board Datasheet 2) "The IC Bus Specification: Version 2.1" Philips Semiconductors, January 2000. http://www.semiconductors.philips.com
36
DS517F2
CS4360
9. PACKAGE DIMENSIONS
28L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
e b2 SIDE VIEW
123
END VIEW
SEATING PLANE
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.03150 0.00748 0.378 BSC 0.248 0.169 -0.020 0 NOM -0.004 0.035 0.0096 0.382 BSC 0.2519 0.1732 0.026 BSC 0.024 4 MAX 0.47 0.006 0.04 0.012 0.386 BSC 0.256 0.177 -0.029 8 MIN -0.05 0.80 0.19 9.60 BSC 6.30 4.30 -0.50 0
MILLIMETERS NOM -0.10 0.90 0.245 9.70 BSC 6.40 4.40 0.65 BSC 0.60 4 MAX 1.20 0.15 1.00 0.30 9.80 BSC 6.50 4.50 -0.75 8
NOTE
2,3 1 1
JEDEC #: MO-153 Controlling Dimension is Millimeters. Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
DS517F2
37

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